The present invention relates to an interface circuit for transmitting a logic signal in a control circuit of a computer or the like, and relates more particularly to an interface circuit of a bus system for carrying out a signal transmission between a plurality of input circuits and output circuits and between input and output circuits, and an interface-network using this interface circuit.
As an interface circuit to be used for a signal transmission between logic elements, there are interface circuits which use ECL (Emitter Coupled Logic), TTL (Transistor Transistor Logic) and CMOS (Complementary Metal Oxide Semiconductor), respectively. These interface circuits have been used differentially to meet specific performance requirements by taking into account circuit speed, power consumption, etc.
Presently, an interface circuit which is to be used mainly for a microprocessor system is required to have performance characteristics such as high-speed operation of at least 100 MHz, low voltage and low power consumption. As a new interface circuit which meets this requirement, an interface circuit called GTL (Gunning Transceiver Logic) has been proposed as disclosed in JP-A-4-225275. This GTL is an interface circuit which meets a terminal voltage of about 1.2 V to 2.0 V at the terminal of the bus-network and a low amplitude of about 1 V for a signal level, to thereby minimize power consumption during a high-speed operation.
In addition, there is U.S. Patent Application based on Japanese Patent Application No. 6-62778, the priority date of which is Mar. 31, 1994 entitled "Data Bus Circuit and Method of Changing over Termination Resistor of the Data Bus Circuit" by Kenji KASHIWAGI, et al. and assigned to the same assignee of this application, also, a U.S. patent application Ser. No. 08/031,854 filed on Mar. 16, 1993 entitled "Bidirectional Signal Transmission Circuit" by Yoshifumi TAKADA, et al and assigned to the same assignee of this application, the contents of which are incorporated herein by reference.